Semiconductor Design Engineer-Digital ASIC/FPGA - Teradyne (California)
Organization & Role
Nextest is a global technology company of Teradyne delivering progressive solutions to complex testing challenges. Without creativity and the diversity of thought, Nextest's technological innovations would not leave the ground. If you are excited at the prospect of joining a global team, that is both exciting and dynamic, then Teradyne may be the place for you!In San Jose, California we are developing test instrumentation for some of the world’s most advanced and highest performance integrated circuits. Our products integrate state-of-the-art digital and analog designs using leading edge ASIC and FPGA technologies, liquid cooling, and high density / high performance signal delivery. We are a small, close-knit team working in an exciting focused atmosphere. We are looking for an experienced Senior FPGA Design Engineer with outstanding technical skills and leadership potential. The candidate should have a strong desire to contribute to a team oriented project where what matters most is our success in bringing products to market quickly with exceptional quality and reliability.
Responsibilities
+ Architect and implement FPGA solutions to support next generation Flash and DRAM test instrumentation.
+ Turn abstract concepts and customer requirements into reliable, extensible, and supportable designs.
+ Assist in the maintenance and extension of existing FPGA designs to support quality improvement and emerging customer requirements.
+ Maintain schedule commitments and deliver high quality end products.
+ Occasional travel may be required.
Basic Qualifications & Skills
Candidate should be an expert with constraint generation for synthesis and timing closure techniques; be familiar with high speed SerDes interfaces, have experience with and high speed memory subsystems. Candidate should have design experience with various FPGAs and/or ASIC technologies. Candidate should also have participated in module/PCBA design and engineering lab checkout. Candidate has acted as technical lead for various design and verification tasks.Additional Skills:Familiarity with automatic semiconductor test equipment and the various subsystems contained within is highly desirable. In particular, an understanding of the integration of ATE subsystems into FPGA designs. Lab experience including use of oscilloscopes, logic analyzers, protocol analyzers preferred.
Education
Bachelors Degree in Electrical Engineering with a minimum of 5 years of relevant work experience or Masters Degree in Electrical Engineering with a minimum of 3 years of relevant experience in ASIC / FPGA Verilog HDL digital logic design techniques and related verification activities.
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Current openings may involve access to export controlled technology and may be subject to export licensing requirements prior to employment. ATTENTION APPLICANTS WITH DISABILITIES: If you’re unable to access our on-line application due to a disability you may visit one of our locations or our Corporate Office at 600 Riverpark Drive, North Reading, MA and request a paper application form. In addition, you may also contact the HR Service Center at 978-370-3041 or contact them at HR.Service.Center@teradyne.com for additional assistance. LitePoint, a Teradyne Company is an equal opportunity employer and all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, age, disability status, protected veteran status, or any other characteristic protected by law. We are a VEVRAA Federal Contractor.
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